The sixth generation of the PCIe specification is right around the corner, as the organization that develops the standard has announced that we are now at version 0.7. This marks the distribution of documentation to interested parties like hardware vendors, so we got to know more about the technical specifications that will characterize the standard.
Most importantly, the data rate is doubled compared to PCIe 5.0, so we are now at 64 Gb/sec (up to 252 GB/s is possible in x16 configuration). This is consistent with the promise to double the data rate between two consecutive generations while maintaining backward compatibility.
PCIe 6.0 will be using the PAM4 (Pulse Amplitude Modulation with four levels) signaling, which greatly reduces channel loss by running at half the frequency with two bits per Unit Interval. It uses similar circuitry and logic as in 8b/10b encoding and 128b/130b encoding, and the backward compatibility isn’t going to be a problem.
Voltage and time margining are going to stay the same as in PCIe 5.0. Finally, the same overall voltage amplitude is going to be retained, but it’s going to spread over more eyes, so each one will have a reduced value.
Another important new thing to be found in PCIe 6.0 is the FEC (Forward Error Correction) system. This will work in cooperation with the Cyclic Redundancy Check (CRC) to detect and correct errors, as well as to improve bandwidth efficiency. For more details about how errors are identified and how their specific position is determined, you may check out this post by the PCI-SIG board member, D. Sharma.
The finalization of the PCIe 6.0 is expected in 2021, but you shouldn’t expect to see any devices supporting it before 2023. Considering that the first DDR5 products are to appear in 2022 and mature (reach higher speeds) in 2023, this is shaping up to be a great year to build your next PC.